Energy-Efficient Runtime Adaptable L1 STT-RAM Cache Design
نویسندگان
چکیده
منابع مشابه
Performance and Energy-Efficient Design of STT-RAM Last-Level Cache
Recent research has proposed having a die-stacked last-level cache (LLC) to overcome the memory wall. Lately, spin-transfer-torque random access memory (STT-RAM) caches have received attention, since they provide improved energy efficiency compared with DRAM caches. However, recently proposed STT-RAM cache architectures unnecessarily dissipate energy by fetching unneeded cache lines (CLs) into ...
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ژورنال
عنوان ژورنال: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
سال: 2020
ISSN: 0278-0070,1937-4151
DOI: 10.1109/tcad.2019.2912920